Memory devices are typically provided as internal, semiconductor, integrated circuits, and/or external removable devices in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change random access memory (PCRAM), and/or flash memory, among others.
Flash memory devices can be utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and/or low power consumption. Uses for flash memory include memory for solid state drives (SSDs), personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players (e.g., MP3 players), and/or movie players, among other electronic devices.
Two types of flash memory array architectures are “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. A NAND array architecture arranges its array of memory cells in a matrix such that the control gates of each memory cell in a “row” of the array are coupled to, and in some cases from, an access line, which is commonly referred to in the art as a “word line”. However each memory cell is not directly coupled to a sense line (which is commonly referred to as a “data line” or a “bit line” in the art) by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a common source and a sense line, where the memory cells commonly coupled to a particular sense line are commonly referred to as a “column” or a “string” in the art.
Memory cells in a NAND array architecture can be programmed to a target (e.g., desired, intended) program state. For example, electric charge can be placed on or removed from a charge storage structure (e.g., a floating gate or charge trap) of a memory cell to put the memory cell into one of a number of program states. For example, a single level cell (SLC) can be programmed to one of two program states (e.g., one bit) so as to represent a binary data value (e.g., “0” or “1”) stored by the memory cell.
Some NAND memory cells can be programmed to one of more than two target program states. Such memory cells may be referred to as multistate memory cells, multiunit cells, or multilevel cells (MLCs). MLCs can provide higher density memories without increasing the number of memory cells because each memory cell can represent more than one bit. A MLC using four program states (e.g., 11, 01, 00, and 10) can use four charge amounts in a floating gate so that the state can be represented by one of four voltage levels such that the MLC can store two bits of data. Generally, N bits per memory cell can be represented using 2N voltage levels. Newer devices may be expected to use eight or more voltage levels. Using a high number of bits per memory cell allows the production of flash devices with high data density and thus reduces the overall cost per flash device. The read operation of a SLC uses one Vt level that is between the “1” and “0” voltage levels (e.g., program states). However, the read operation of a MLC with four states uses three Vt levels, an MLC with eight states uses seven Vt levels, and a memory cell that stores N bits per memory cell, represented by 2N states, uses 2N-1 Vt levels for read operations.
A NAND array architecture that includes a large number of memory cells with multiple bits per memory cell can be expected to have a range of actual Vt levels for each program state based upon statistical variation. The range of actual Vt levels for each program state may result from random variation in manufacturing and/or programming of the memory cells, in erasing a memory cell prior to being reprogrammed, which can inherently broaden a voltage level range stored by each memory cell for each program state, among other causes. With continued increase in complexity, miniaturization, etc., of NAND technology, along with the number of bits programmed per memory cell, the reliability and/or endurance of NAND memory cells may be decreasing, at least partially by variability in the actual threshold voltages for the program states relative to predetermined reference (e.g., sense and/or read) voltages.